What will be the next value of the counter if: the current value of it is 3'b110, a positive edge of the clock signal and, a positive edge of reset signal happens? Explain your answer in detail. Modify the code so that it creates a 3 bit down counter that counts from 111 down to 000. Display clock signal, the outputs of the counter (Q and Qo), and output waveform on the analyzers. You may group the inputs on the MUX as per your choice. route to the Part 2: Use this sequence as inputs to the selection bits of the MUX, generate the given two waveforms. What's the condition for which the counter will reset its value? What are the conditions that should be fulfilled so that we reset the counting process? 7. Implement the logic circuit for the input equations using any gates. Modify the code so that it creates a 4 bit up counter that counts from 0000 up to 1010. What happens if the positive edge of the clock and the positive edge of the reset signal happen at the same time? 6. What's the initial value of the counter in binary and decimal numbering system? 5. The image above shows the two flip flops linked together and the 4 binary sequences on the LEDs in this circuit. What does the given code do: up or down counter? Explain. The output of the first LED connects via a NOT gate to the input of the second flip flop. How many ports does this module have? Mention their names and their purpose. 9 - Verilog Code for 2 bit up counter 1 module my_counter (clk, reset, counter_out) input clk, reset output counter_out reg counter_up = 2'b00 always clk, negedge reset) begin if(!reset) counter_up <= 2'b00 else counter_up <= counter_up + 2'b01 10 11 12 12 13 14 15 16 17 endmodule 1 Counters end assign counter_out= counter_up Copyright © American College of the Middle East.
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